The voltage identification (VID) of a modern central processing unit (CPU) is highly dynamic and changes very quickly from low to high and from high to low. A CPU VID transient may occur successively in a very short period, which results in the performance of the computer is not entirely relied on CPU's capability but also depends on the VID chasing speed of the voltage regulator. The CPU will compute the given job only when the output voltage of the voltage regulator settled to the desired VID. In other words, if the VID chasing speed of the voltage regulator cannot meet the given spec, the CPU might be damaged caused by the unsatisfied voltage or will become idle and decline the system's performance critically.
As to an adaptive voltage position (AVP) system, the voltage regulator will generate a current sense signal according a sensed inductor current and then provide a droop control signal according to the generated current sense signal to regulate the output voltage. Referring to FIG. 1A and FIG. 1B, status views of the current sense signal and the output voltage respectively in the situations of VID transient up and VID transient down are shown. It can be found from the VID transient up period of the VID value changing from VID1 to VID2 in FIG. 1A or the VID transient down period of the VID value changing from VID2 to VID1 in FIG. 1B that, the inductor current IL would have extra increase or decrease resulting from the change of VID value, which results in the current sense signal VCS0 increased or decreased correspondingly and thereby the average value of the output voltage VOUT during the transient up or down period is non-linearly changed consequently. Accordingly, the actual settling time Ta of the output voltage VOUT is out of the given settling time spec Ts in the transient up or down period.